This section provides background information related to the present disclosure which is not necessarily prior art.
FIG. 1 is a view of an example of a conventional III-nitride semiconductor light-emitting device. The III-nitride semiconductor light-emitting device includes a substrate 100, a buffer layer 200 grown on the substrate 100, an n-type nitride semiconductor layer 300 grown on the buffer layer 200, an active layer 400 grown on the n-type nitride semiconductor layer 300, a p-type nitride semiconductor layer 500 grown on the active layer 400, a p-side electrode 600 formed on the p-type nitride semiconductor layer 500, a p-side bonding pad 700 formed on the p-side electrode 600, an n-side electrode 800 formed on the n-type nitride semiconductor layer 300 exposed by mesa-etching the p-type nitride semiconductor layer 500 and the active layer 400, and a protection film 900.
In the case of the substrate 100, a GaN substrate can be used as a homo-substrate. A sapphire substrate, a SiC substrate or a Si substrate can be used as a hetero-substrate. However, any type of substrate that can have a nitride semiconductor layer grown thereon can be employed. In the case that the SiC substrate is used, the n-side electrode 800 can be formed on the surface of the SiC substrate.
The nitride semiconductor layers epitaxially grown on the substrate 100 are usually grown by metal organic chemical vapor deposition (MOCVD).
The buffer layer 200 serves to overcome differences in lattice constant and thermal expansion coefficient between the hetero-substrate 100 and the nitride semiconductor layers. U.S. Pat. No. 5,122,845 describes a technique of growing an AlN buffer layer with a thickness of 100 to 500 Å on a sapphire substrate at 380 to 800° C. In addition, U.S. Pat. No. 5,290,393 describes a technique of growing an Al(x)Ga(1-x)N (0≦x<1) buffer layer with a thickness of 10 to 5000 Å on a sapphire substrate at 200 to 900° C. Moreover, PCT Publication No. WO/05/053042 describes a technique of growing a SiC buffer layer (seed layer) at 600 to 990° C., and growing an In(x)Ga(1-x)N (0<x≦1) thereon. In particular, there is provided with an undoped GaN layer with a thickness_of 1 micron to several microns (μm) on the AlN buffer layer, the Al(x)Ga(1-x)N (0≦x<1) buffer layer or the SiC/In(x)Ga(1-x)N (0<x≦1) layer.
In the n-type nitride semiconductor layer 300, at least the n-side electrode 800 formed region (n-type contact layer) is doped with a dopant. In a particular embodiments, the n-type contact layer is made of GaN and doped with Si. U.S. Pat. No. 5,733,796 describes a technique of doping an n-type contact layer at a target doping concentration by adjusting the mixture ratio of Si and other source materials.
The active layer 400 generates light quanta by recombination of electrons and holes. For example, the active layer 400 contains In(x)Ga(1-x)N (0<x≦1) and has a single layer or multi-quantum well layers.
The p-type nitride semiconductor layer 500 is doped with an appropriate dopant such as Mg, and has p-type conductivity by an activation process. U.S. Pat. No. 5,247,533 describes a technique of activating a p-type nitride semiconductor layer by electron beam irradiation. Moreover, U.S. Pat. No. 5,306,662 describes a technique of activating a p-type nitride semiconductor layer by annealing over 400° C. PCT Publication No. WO/05/022655 describes a technique of endowing a p-type nitride semiconductor layer with p-type conductivity without an activation process, by using ammonia and a hydrazine-based source material together as a nitrogen precursor for growing the p-type nitride semiconductor layer.
The p-side electrode 600 is provided to facilitate current supply to the p-type nitride semiconductor layer 500. U.S. Pat. No. 5,563,422 describes a technique associated with a light-transmitting electrode composed of Ni and Au and formed almost on the entire surface of the p-type nitride semiconductor layer 500 and in ohmic-contact with the p-type nitride semiconductor layer 500. In addition, U.S. Pat. No. 6,515,306 describes a technique of forming an n-type superlattice layer on a p-type nitride semiconductor layer, and forming a light-transmitting electrode made of indium tin oxide (ITO) thereon.
The p-side electrode 600 can be formed thick as to not transmit but rather to reflect light toward the substrate 100. This technique is called the flip chip technique. U.S. Pat. No. 6,194,743 describes a technique associated with an electrode structure including an Ag layer with a thickness over 20 nm, a diffusion barrier layer covering the Ag layer, a bonding layer containing Au and Al, and covering the diffusion barrier layer.
The p-side bonding pad 700 and the n-side electrode 800 are provided for current supply and external wire bonding. U.S. Pat. No. 5,563,422 describes a technique of forming an n-side electrode with Ti and Al.
The optional protection film 900 can be made of SiO2.
The n-type nitride semiconductor layer 300 or the p-type nitride semiconductor layer 500 can be constructed as a single layer or as plural layers. Vertical light-emitting devices are introduced by separating the substrate 100 from the nitride semiconductor layers using a laser technique or wet etching.
FIG. 2 is a view of an example of a III-nitride semiconductor light-emitting device described in PCT Publication No. WO/2008/026902. The III-nitride semiconductor light-emitting device includes a substrate 110, a buffer layer 210, an n-type III-nitride semiconductor layer 310, an active layer 410, a p-type III-nitride semiconductor layer 510, a p-side electrode 610, a p-side bonding pad 710, a first n-side electrode 810a, a second n-side electrode 810b, and an opening 910. The substrate 110 is formed of sapphire and has a groove 120 formed therein.
The opening 910 is formed on the groove 120 along and through the plurality of III-nitride semiconductor layers 210, 310, 410 and 510, the optional first n-side electrode 810a is formed on the n-type III-nitride semiconductor layer 310 in the opening 910, and the second n-side electrode 810b is brought into contact with the n-type III-nitride semiconductor layer 310 through the groove 120, such that the III-nitride semiconductor light-emitting device becomes a vertical light-emitting device. Here, the optional first n-side electrode 810a serves to ensure contact between the second n-side electrode 810b and the n-type III-nitride semiconductor layer 310.
The light-emitting device as described in PCT publication No. WO/2008/026902 has a disadvantage in that, since the groove 120 and the opening 910 penetrate through the light-emitting device, a material such as epoxy may go up from the bottom of the light-emitting device during fabrication of the package. This light-emitting device also has the disadvantage that a process for bonding a wire to the p-side bonding pad 710 is necessary during fabrication of the package, subsequently increasing the size of the package because the bonded wire should be sufficiently wrapped in order to be protected.